
`include "defines.v"

//----------------------------------------------------------------
//Module Name : IFID_reg.v
//Description of module:
//
//----------------------------------------------------------------
//Designer:	Tang Pengyu
//Date: 2021/9/27/17:14	  
//----------------------------------------------------------------

module	IFID_reg(
	input	clk,
	input	ifid_rst,
	input	ifid_ena,
	
//	input	i_if_time_intr_r,
	input	i_if_inst_ena,
	input	[`INST_LEN-1:0]	i_if_inst,
	input	[`INST_ADDR_LEN-1:0] i_if_pc_out,
	input	i_if_fetched,
	input	[`INST_ADDR_LEN-1:0] i_if_addr,
	
//	output	reg	o_if_time_intr_r,
	output	reg	o_if_inst_ena,
	output	reg	[`INST_LEN-1:0] o_if_inst,
	output	reg	[`INST_ADDR_LEN-1:0] o_if_pc_out,
	output	reg	o_if_fetched,
	output	reg	[`INST_ADDR_LEN-1:0] o_if_addr
	);
	
always @(posedge clk)	begin
	if(ifid_rst)	begin
//		o_if_time_intr_r <= 1'b0;
		o_if_inst_ena <= 1'b0;
		o_if_inst <= `INST_NOP;
		o_if_pc_out <= {`INST_ADDR_LEN{1'b0}};
		o_if_fetched <= 1'b0;
		o_if_addr <= {`INST_ADDR_LEN{1'b0}};
	end
	
	else if(ifid_ena)	begin
//		o_if_time_intr_r <= i_if_time_intr_r;
		o_if_inst_ena <= i_if_inst_ena;
		o_if_inst <= i_if_inst;
		o_if_pc_out <= i_if_pc_out;
		o_if_fetched <= i_if_fetched;
		o_if_addr <= i_if_addr;
	
	end

end


endmodule